Mentor Graphics Boosts Scalability of the ADVance MS Mixed-Signal Functional Verification Platform
WILSONVILLE, Ore.—(BUSINESS WIRE)—Feb. 9, 2004—
Mentor Graphics Corporation (Nasdaq:MENT) today
announced the availability of ADVance MS(TM) (ADMS) version 4.0. By
adding support for SystemVerilog and SystemC languages, Mentor has
reinforced the position of ADMS as the most scalable platform
available for mixed-signal functional verification. ADMS 4.0 also
contains expanded tool capabilities that enable designers to verify
that their designs are functioning to the original specification in
either a digital-centric or analog-centric design flow.
ADMS version 4.0 now delivers full language support for
SystemVerilog, SystemC VHDL, Verilog, SPICE, VHDL-AMS, Verilog-AMS and
C. Support for eight languages gives users the ability to perform
block-level validation and full-chip functional verification in a
single simulation environment from the system specification stage to
the post-layout verification stage.
With ADMS 4.0, Mentor is delivering a single common platform to
extend both digital verification and analog verification for
mixed-signal designs. It enables digital centric verification such as
testbenches (directed testing and pseudo random testing). It enables
analog centric verifications such as circuit simulation (DC, AC,
Transient, Parametric, Monte Carlo and Corner), and it also enables
mixed-signal centric verification such as 'checkerboard' analysis.
With this common verification platform, ADMS 4.0 enables concurrent
top down design and bottom up verification of AMS SoC designs.
ADMS 4.0 also integrates with Verisity SpecMan Elite to facilitate
the complex verification strategies required for new mixed-signal
designs. This integration enables early verification of the
architectural or partitioning decisions being made, and can be reused
as testbenches throughout the design process. These allow fundamental
design flaws to be discovered and then corrected early and easily.
For global companies utilizing geographically dispersed design
teams, ADMS offers each team the ability to perform block-level
verification in their preferred language. When blocks are brought
together for full-chip implementation, including intellectual property
(IP) from other sources, ADMS can be used for final, full-chip
verification while preserving design elements in their native
language. This alleviates the risk of data compatibility and integrity
problems and uncovers functional flaws that can occur when using
multiple verification tools. Additionally, ADMS integrates seamlessly
with any design flow, delivering unmatched flexibility regardless of
existing tools.
"ADVance MS is the original multi-language, multi-level simulator
for analog, mixed-signal and RF designs," said Jue-Hsien Chern, vice
president and general manager, deep submicron division, Mentor
Graphics. "We've got years of technology research and customer
collaboration behind the development of this platform. With the
addition of SystemVerilog and SystemC support, Mentor furthers its
leadership position in delivering scalable verification solutions."
Pricing and Availability
Pricing for ADVance MS 4.0 starts at US $110,000 in North America,
and will be available in Q2, 2004 for Linux, HP and Sun platforms.
Mentor Graphics ADVance MS Simulation Technology
The Mentor Graphics ADVance MS (ADMS) tool is a single-kernel,
language-independent functional verification environment for digital,
analog, mixed-signal and RF circuits. This platform is built upon four
high-performance, customer-proven simulation technologies: Eldo(TM)
for analog, ModelSim(R) for digital, Mach for transistor-level, and
Eldo RF for radio frequency simulations. The ADMS platform is a
mature, five-year-old functional verification environment, which is
currently in use in more than a hundred customer sites.
About Mentor Graphics
Mentor Graphics Corporation (Nasdaq:MENT) is a world leader in
electronic hardware and software design solutions, providing products,
consulting services and award-winning support for the world's most
successful electronics and semiconductor companies. Established in
1981, the company reported revenues over the last 12 months of about
$675 million and employs approximately 3,700 people worldwide.
Corporate headquarters are located at 8005 S.W. Boeckman Road,
Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are
located at 1001 Ridder Park Drive, San Jose, California 95131-2314.
World Wide Web site: http://www.mentor.com/.
Mentor Graphics and ModelSim are registered trademark and ADVance
MS and Eldo are trademarks of Mentor Graphics Corporation. All other
company or product names are the registered trademarks or trademarks
of their respective owners.
Contact:
Mentor Graphics
Carole Thurman, 503-685-4716
carole_thurman@mentor.com
or
Weber Shandwick
Emily Taylor, 503-552-3733
etaylor@webershandwick.com
